The present invention relates to a semiconductor device and a method for fabricating the same and, more particularly, to a MIS (metal insulator semiconductor) transistor having an extension structure and further having an LDD (lightly doped drain) structure in the source and drain regions thereof.
In recent years, MIS-type analog-digital mixed LSIs (large scale integrated circuits) have been used to control electronic equipment. To provide a MIS-type analog-digital mixed LSI featuring higher-speed operation and higher integration, a CMIS (complementary MIS) analog circuit technology has been becoming important.
In a CMIS analog circuit, the current gain gradually attenuates as the operational frequency is increased during RF operation so that it is effective to hold the current gain of the transistor high for a higher-speed operation.
In a semiconductor device disclosed in Japanese Laid-Open Patent Publication No. 2000-208605, an implantation region (hereinafter referred to as a pocket implantation region) having a polarity opposite to that of an LDD structure is provided under the LDD structure, thereby increasing the output impedance and improving the current gain.
To improve the current gain, it is effective to form a shallow LDD region and thereby completely deplete even the portion of a channel region in a semiconductor substrate which is located below the drain-side end portion of a gate electrode.
However, since an impurity is normally implanted into the pocket implantation region by using the gate electrode as a mask, it is difficult to implant the impurity into a shallow portion below the end portion of the gate electrode such that the conductivity type of the LDD region is cancelled out. Accordingly, the problem is encountered that complete depletion is hard to achieve.